1. Field of the Invention
The present invention relates to a solid-state imaging device and particularly to the structure of a readout gate section of a unit pixel of a solid-state imaging device.
2. Description of the Related Art
FIG. 1 shows the configuration of an interline transfer CCD (charge coupled device) solid-state imaging device as an example of solid-state imaging devices.
As shown in FIG. 1, an effective pixel section 101 is constituted of a plurality of photosensors 102 and a plurality of vertical CCD registers 103. The photosensors 102 are arranged two-dimensionally in matrix form, each of which converts incident light to a signal charge of a charge amount corresponding to the quantity of the incident light and stores the signal charge. Each vertical CCD register 103 is provided for the associated vertical column of the photosensors 102 and vertically transfers signal charges that are read out from the respective photosensors 102 via respective readout gate sections (not shown).
Signal charges that have been read into the vertical CCD registers 103 are shifted into a horizontal CCD register 104 by portions corresponding to one scanning line (one line) in part of a horizontal blanking period. The signal charges of one scanning line are sequentially transferred in the horizontal direction in the horizontal CCD register 104 and then converted to an output signal voltage by, for example, a charge detection section 105 having the floating diffusion amplifier configuration.
FIG. 2 is a plan pattern diagram showing the configuration of one photosensor 102 and its peripheral portion (region A in FIG. 1). FIG. 3 shows a sectional structure taken along line Y-Y' in FIG. 2 and FIG. 4 shows its potential profile.
In the photosensor 102, a storage/readout control on a signal charge produced by photoelectric conversion is performed by a potential variation at a readout gate section 106 that exists between the photosensor 102 and the vertical CCD register 103. Since a first-layer transfer electrode 107-1 of the vertical CCD register 103 also serves as a gate electrode 108 of the readout gate section 106, vertical transfer pulses V.phi. take 3-value levels.
That is, as shown in a waveform diagram of FIG. 5, repetitive pulses having a low level V.phi.L and a high level V.phi.H serve as vertical transfer pulses that are applied to the transfer electrodes 107-1 and 107-2 of the vertical CCD register 103. Pulses having a level V.phi.T that is even higher than the high level V.phi.H serve as readout clock pulses that are applied to the gate electrode 108 of the readout gate section 106. As a result, the gate potential of the readout gate section 106 becomes V.phi.T during the signal charge readout period and repeatedly becomes V.phi.L and V.phi.H during the transfer period of the vertical CCD register 103.
The potential of the region under the gate electrode 108 of the readout gate section 106 should have a proper value with respect to the prescribed readout clock voltage V.phi.T during the signal charge readout period and with respect to the high level V.phi.H of vertical transfer pulses during the non-readout period, that is, the transfer period of the vertical CCD register 103.
This is for the following reasons. In the signal charge readout period, a potential profile as shown in FIG. 6(A) should be established to assure complete signal charge readout. In the transfer period of the vertical CCD register 103, signal charge leakage to the vertical CCD register 103 as shown in FIG. 6(B) should absolutely be prevented even when the potential of the gate electrode 108 is at the high level V.phi.H.
In setting the above potential values, the misregistration of photomask patterns should be prevented that may cause the above-mentioned leakage of stored charge and readout failure, an insufficient amount of charge handled and a transfer failure of the vertical CCD register 103, increases in the rates of those failures due to dispersion, and so forth.
However, if a mask dedicated to the readout gate sections 106 is used in setting the potential of the readout gate sections 106, it is difficult to freely adjust the impurity concentration and the mask patterns to the readout gate sections 106 because of small sizes of the mask patterns and other factors. Therefore, the potentials of the readout gate sections 106 and the photosensors 102 cannot be set at optimum values, causing the above-mentioned problems due to misregistration of mask patterns.
The problems due to misregistration of mask patterns will be described below. First, if the region of the readout gate section 106 deviates to the vertical CCD register 103 side as shown in FIG. 7(A), the effective width of the vertical CCD register 103 decreases as shown in FIG. 7(B), which may cause a reduction in the amount of charge handled, a transfer failure, and other failures. Further, the failure rate increases due to dispersion.
If the region of the readout gate section 106 deviates to the photosensor 102 side as shown in FIG. 8(A), the gate length of the gate electrode 108 is shortened as shown in FIG. 8(B), which may increase the rate of the failure of leakage of signal charge stored in the photosensor 102 and cause a reduction in the sensitivity of the photosensor 102 and other problems. Further, the failure rate increases due to dispersion.
On the other hand, as for the patterns of the vertical CCD registers 103 and the horizontal CCD register 104, an impurity is implanted simultaneously to the CCD registers 103 and 104 by using the same mask to prevent a failure in transferring signal charges from the vertical CCD registers 103 to the horizontal CCD register 104 due to misregistration of photomasks and other failures.
For example, if the impurity regions of the vertical CCD registers 103 deviate to the horizontal CCD register 104 side, the potential of the connecting portion of the registers 103 and 104 becomes deep locally as shown in FIG. 10(A). If gaps are formed between the vertical CCD registers 103 and the horizontal CCD register 104, the potential of the gap portions becomes shallow locally as shown in FIG. 10(B). These potential profiles may cause the above-mentioned transfer failure and other failures.
If impurity implantation is performed at the same concentration at the same time by using the same mask for the vertical CCD registers 103 and the horizontal CCD register 104 as descried above to prevent the transfer failure and other failures, it is difficult to provide an optimum potential for each of the vertical CCD registers 103 and the horizontal CCD register 104. This may result in a transfer failure, an insufficient amount of charge handled, and other failures.